1. Field of Invention
The present invention is related to semiconductor nonvolatile memory and in particular to program and program verify for twin MONOS flash memories.
2. Description of Related Art
In MONOS flash memory devices, data is stored as electrons in the nitride region of an oxide-nitride-oxide (ONO) composite layer under a control gate. The presence of electrons in the nitride region increases the threshold of the device. An erased cell with a logical xe2x80x9c1xe2x80x9d stored has few or no stored electrons in the nitride region, and a programmed cell with a logical xe2x80x9c0xe2x80x9d stored has a fixed range of electrons in the nitride region. In conventional MONOS memories, the program operation is interrupted by program verify cycles in order to control the number of electrons in the nitride region. A state diagram of prior art for a program operation with program verify is shown in FIG. 1. In the first program setup 101 is needed to startup the charge pumps and setup the voltages needed for the program operation. The selected memory cell is subjected to program voltage conditions during the program pulse step 102. After a fixed time, the threshold of the memory cell is tested in the program verify step 03. If the threshold of the memory cell is greater than the reference threshold, then the memory cell is deemed to have been programmed, and program is complete 104. Otherwise if the threshold of the selected memory cell is not high enough, then the memory cell is placed back into the program state 102.
FIG. 2a gives an example of voltage conditions of a MONOS memory cell of prior art for program and for program verify of prior art in FIG. 2b. The memory cell is composed of a control gate 202, a source 201 and a drain 203. Electrons are stored in the nitride region 204 under the control gate 202. It should be noted that the voltages that are shown are an example only. Actual voltages depend on many specifications such as program speed, oxide thickness, and memory cell dimensions. For CHE (channel hot electron) injection program, a voltage of approximately 10V is applied to the control gate 202 and another high voltage of approximately 5V is applied to the drain 203 with the source 201 grounded.
Referring to FIG. 2b, program verify is very similar to a read operation, in that one diffusion will be measured with respect to a reference to determine the memory state. The control gate 202 is biased to approximately 2V, the drain 201 is biased to approximately 1V and the source 203 is biased to 0V. Whenever there is a transition between program and program verify states, it is necessary to swap the source and drains and to lower the drain 203 voltage from 5V to 0V. If another program cycle is necessary, the drain 203 is raised to 5V again. This is an inefficient usage of charge, because extra current is needed to raise and lower the drain voltage between program and program verify cycles. When the drains of many memory cells are connected to a single highly capacitive bit line, the transition time between program and program verify increases. This increased transition time increases the overall program operation time.
FIG. 3 shows a prior art dual storage MONOS memory device (called NROM) in which there are two memory storage sites 304 and 305 within one memory cell, described in U.S. Pat. No. 6,011,725 (Eitan), which is directed to a method of read described called xe2x80x9creverse readxe2x80x9d. The diffusion 303, which is closest to the, selected memory storage region 305, becomes the lower voltage or source whereas the diffusion 301, which is opposite the selected memory storage region 305, becomes the higher voltage or drain. The drain voltage is higher than the source voltage in order to create a depletion region into the substrate and thus xe2x80x9coverridexe2x80x9d the charge that may be stored in the unselected memory storage region, if it is in the high threshold xe2x80x9c0xe2x80x9d memory state. This type of NROM memory cell can only operate in reverse read mode, because a higher voltage is needed on the unselected memory storage side to override the unselected memory channel. If the device were to be read in the forward direction, then the higher drain voltage would override the selected memory storage side, and the cell would always be sensed to be in a low Vt xe2x80x9c1xe2x80x9d memory state.
Another prior art dual storage MONOS device is described in patent application Ser. No. 09/426,692, filed Oct. 25, 1999, called the twin MONOS cell and shown in FIG. 4a. In this type of memory cell there are two extra side wall polysilicon control gate structures 406 and 407 in addition to the word gate 402 and two diffusions 401 and 403. Unlike the control gate 302 of FIG. 3, the word gate 402 of FIG. 4a does not have memory nitride storage regions underneath itself. Instead, the memory storage regions lie underneath the side wall polysilicon control gates 406 and 407. As shown in FIG. 4a, two side wall polysilicon gates between two adjacent memory cells are electrically connected together to define one equivalent control gate. Because the additional control gates 406 and 407 provide another level of flexibility, the twin MONOS cell can be easily read in both the reverse and forward directions. The channel underneath of the unselected nitride storage site can be overridden by increasing the voltage of the associated control gate to a voltage which is some delta above the highest possible threshold voltage (Vcg override). Although the twin MONOS cell is able to read in both directions, the forward read has slower read performance, due to lower cell current, smaller threshold margins, and limited voltage range. FIG. 4b shows the relationship of drain voltage v.s. the threshold of the selected nitride region for memory nitride channel lengths of  greater than 50 nm and  less than 50 nm. It can be seen that during forward read, the high Vt cell (xe2x80x9c0xe2x80x9d) suffers degradation of threshold at higher drain-source voltages. This effect becomes more severe for shorter channel lengths. Thus it is desirable to keep the drain voltage to lower than approximately 0.3xcx9c0.5V during sensing in order to maintain reasonable threshold margin between the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d cell.
FIG. 4c is a schematic representation of the twin MONOS cell array in the diffusion bit configuration. Each memory cell consists of one word gate, two control gate halves, under which each control gate half is one nitride storage region, and two diffusion halves. In this array, memory cells are arranged in rows and columns, in which word gates are horizontally connected together by word lines WL[0-1], and bit diffusions are vertically connected together by bit lines BL[0-3], and control gates are vertically connected together by control lines CG[0-3]. Control lines CG[0-3] and bit lines BL[0-3] may run atop of one another and have a coupling capacitance of about 30%.
For high bandwidth program applications, it is desirable to program many memory cells in parallel. If many bit lines and control lines are need to be charged and discharged between program and program verify cycles, the voltage and current requirements of the charge pumps and voltage regulators will be very high, which impacts power and overall program time. In multi-level storage memories especially, the number of program and program verify cycles is greater in order to have tighter control between threshold states. Thus it is desirable to minimize the voltage transitions between program and program verify.
It is an objective of the present invention to provide a low power method of programming a dual storage site MONOS memory cell.
It is also an objective of the present invention to provide a method of program verify for a dual storage site MONOS memory cell.
It is still an objective of the present invention to efficiently switch between program and program verify operations.
It is another objective of the present invention to minimize transition between program and program verify by minimizing the charging and discharging the diffusion bit line.
It is another objective of the present invention to minimize transistion between program and program verify by minimizing the charging and discharging of control gate voltages.
It is another objective of the present invention to minimize the number of reference voltages required for program and program verify.
It is also another objective of the present invention to use forward read for program verify.
It is also another objective of the present invention to use reverse read for program verify.
It is another objective of the present invention to use capacitive coupling between the control gate line and the bit line in order to achieve a target threshold voltage by minimal voltage application to the control lines and bit lines.
It is another objective of the present invention to protect the adjacent cell from program disturb.
It is still another objective of the present invention to control program cell current by connecting a load transistor to the source diffusion.
It is yet an objective of the present invention to maintain control gate voltages for program and program verify to be the same.
In the present invention a method to produce a fast switch between program and program verify is described for a MONOS memory device. The word gate of the cell to be programmed is biased to a low voltage to limit memory cell current to a few microamperes. The drain diffusion is biased to a high voltage and the source diffusion is grounded. The drain diffusion is the diffusion near the storage site to be programmed in a two storage site device. The storage site is a nitride region located below a control gate. In a two storage site device there are two control gates and two separate nitride regions. The unselected control gate is biased to a high voltage to override the highest possible threshold voltage of the memory storage region beneath the unselected control gate. The selected control gate is the control gate above the storage site to be programmed and is biased to a high voltage for electron injection into the nitride storage site. The source diffusion can be connected to a load device to limit and control cell current, and cell current can be controlled with a low word gate voltage. To control program disturb of the adjacent cell, the voltage of the unselected diffusion of the adjacent cell is increased slightly. Increasing the voltage of the unselected adjacent diffusion decreases the gate to source voltage as well as increases the threshold voltage of the adjacent storage region and protects the cell from program disturb.
In order to program a memory cell of the present invention a program verify operation is necessary to determine if the cell being programmed has reach a sufficient program voltage. To do this there is a minimum of one switch from the program operation to a program verify operation and back. There can be several switches between operations during the programming of a cell. If the voltages involved in the two operations are substantially dissimilar, there is considerable charging and discharging of the various connecting lines, which results in time delays. To minimize the time delays between the two operations the bit line voltages and the control gate voltages are made the same as much as possible during both program and program verify. Also one variation of program verify uses a xe2x80x9cforward readxe2x80x9d direction which puts the lower voltage on the diffusion opposite the selected nitride storage site. The xe2x80x9cforward readxe2x80x9d operation allows minimal charging and discharging of the bit lines and control gates. This forward read approach is most effective when the channel length under the nitride region is long and the threshold voltage reduction as a function of drain-source voltage, shown in FIG. 4b, is small.
In order to program verify a selected nitride region in a twin MONOS memory cell, the source and drain bit lines are equalized to a voltage that is half of the high drain voltage during program. At the same time, the selected control gate voltage is lowered slightly, and the word line is then raised to a higher voltage to allow the word gate channel to conduct. Finally, one of the two bit lines is pulled down to a lower voltage. A sense amplifier connected to the bit line monitors the other bit line with respect to a reference voltage; if the target nitride region has been programmed enough, the voltage will be maintained, otherwise it will also fall. Verify can be performed in both the forward and reverse directions by choosing which of the two bit lines to pull down, or connect to the sense amplifier.
Another program method is described in which program is performed by utilizing the capacitance of the BL. Due to the high injection efficiency of the channel hot electron (CHE) program for the twin MONOS memory, program can be sufficiently completed within a short time, by using the charge stored on the capacitance of the high voltage drain side bit line. Program verify is performed by utilizing capacitance of the BL and the coupling capacitance between the bit lines and the control gate lines in order to increase the threshold voltage range. First the appropriate voltages are applied to the control gate lines and bit lines for the program. The control gate lines and bit lines are then floated and the word line is raised to a low voltage to limit the program current. When the word line turns on, all channels between the source and drain are on, so that charge will flow between the two bit lines. However, the low voltage of the word line also limits the source bit line voltage. When the drain side bit line voltage falls past a certain point, injection will stop. In order to program verify, the word line is raised to a high voltage in order for both bit lines to equalize to a middle voltage. Thereafter, the bit line closest to the selected nitride region will be pulled down to a lower voltage. The threshold of the verify operation is determined by the control gate voltage of the selected side minus the lower bit line voltage. The voltage of the opposite bit line may be monitored to determine whether the selected nitride region has been programmed enough such that the bit line voltage is maintained, and doesn""t fall.
The program to program verify sequences described in the present invention may also be applied to high program bandwidth applications for storage of multiple threshold levels in a single nitride region.